The present invention relates to phase-lock loops. Specifically, the invention relates to a phase-lock loop implemented in a complementary metal oxide semiconductor structure. The invention also relates to use of the phase-lock loop in an apparatus to extract an embedded clock in a Manchester-encoded data stream.
Manchester-encoded data, also referred to as a bi-phase signal, results from combining a clock signal with binary data through use of an Exclusive OR function. Encoding 10 megahertz data, for example, in this way produces a data stream having both 5 megahertz (MHz) and 10 MHz signals. The definition of Manchester-encoded data does not restrict an encoding frequency to 10 megahertz. A network which conforms to an IEEE 802.3 Standard requires an encoding frequency of 10 megahertz. A preferred embodiment of the present invention is useful for such a network.
Manchester-encoded data always has a transition in what as referred to as a bit-cell center. Other transitions may or may not occur at a bit cell boundary, depending on the data type. Therefore, it may be said that Manchester-encoded data has signal components at the data rate (10 megahertz, for example) and one half of the data rate (5 megahertz, for example)
To decode this Manchester-encoded data, a detector extracts the embedded clock signal. Combining the extracted clock signal with the encoded signal by forming the Exclusive OR logical sum, reproduces the data. Thereafter, the data and the clock signal are available. Extracting the clock requires that the data of the encoded Manchester signal be sampled in the second half of the bit cell, that is after the bit cell center. The Manchester-encoded signal includes an embedded clock signal, such as 10 megahertz. However, variation in this embedded clock signal will occur. The variation causes uncertainty in the sampling point of the encoded data.
Phase-lock loops track variations in frequency of an input signal. Phase-lock loops are used in circuitry to extract the clock from the Manchester signal. Since the valid Manchester-encoded data has both 5 MHz and 10 MHz components, conventional phase-lock loops cannot properly track the data. That is, if the phase-lock loop receives a succession of 10 MHz pulses followed by a 5 MHz pulse, the phase-lock loop attempts to track the 5 MHz and correct itself. If the 5 MHz pulse is followed by a 10 MHz pulse, the phase-lock loop again tries to correct itself. Alternation of the 5 and 10 MHz pulses results in the phase-lock loop trying to track the changing signal. Phase-lock loops have a characteristic known as bandwidth. The greater a bandwidth, the faster the phase-lock loop can respond to variations in an input signal's frequency. The smaller the bandwidth, the more stable and resistant to change is the phase-lock loop. It is possible with a large bandwidth, that inherent jitter in an encoded Manchester signal can combine with a fluctuating phase-lock loop to cause random sampling of the encoded Manchester signal. Random sampling of the Manchester signal results in incorrect data acquisition providing faulty operation. Therefore, use of small bandwidth circuits relatively immune to changes in input frequency provide insensitivity to frequency fluctuations and remain locked onto nominal 10 MHz components.
Conventional timing circuits frequently use one-shot circuits. Often, a starting edge of a pulse initiates an event. It is desirable to register receipt of a corresponding stop pulse. It is also desirable to register an excessive amount of elapsed time, indicating failure to receive a stop pulse. This one-shot timing is not conveniently done by use of clock signals. A problem results from the fact that many manufactured products cannot simultaneously compensate for voltage, current and capacitance differences which vary independently in these timing circuits. These variations occur from device to device and transistor to transistor of each device. A solution typically uses constant current sources because of the known relationship between current and capacitance represented by: dv/dt=i/C. If a constant current flows into a fixed capacitance, then a change of voltage over time will be constant. Phase-lock loop timing circuits having stable frequencies control these current sources to provide accurate timing. Therefore, variation in a phase-lock loop can disrupt timing sequences controlled by regulated current from the phase-lock loop. Therefore, variation in phase-lock loops are not desired.
A second problem in phase-lock loops, especially those having the desired narrow bandwidth, is that they usually have a slow acquisition time constant. An acquisition time constant is an indication of how long it takes for a phase-lock loop to adjust itself to coincide with an input frequency. The amount of time a phase-lock loop would take to go from 0 Hz frequency to 10 MHz is determinable in a well-known fashion. However, this finite amount of time is typically many orders of magnitude too long for use in devices decoding 10 MHz Manchester data corresponding to the IEEE specification 802.3. This specification is hereby expressly incorporated by reference. The IEEE specification 802.3 clearly identifies a maximum amount of time which a decoding device may add to a received data stream before it may output valid data. Most devices with a narrow bandwidth have a slow acquisition time which would add unacceptable amount of delay to decoding of data. As acquisition times become longer, introduced delays may be of sufficient magnitude that an entire manchester-encoded packet may be fully received and terminated before proper acquisition and decoding of the data by the phase-lock loop. Therefore, there is an inherent tension between a narrow bandwidth requirement and a fast acquisition time constant. The necessary fast acquisition time constant ensures that a phase-lock loop almost immediately locks onto the incoming signal. U.S. Pat. No. 4,565,976 to Campbell describes an interruptable voltage-controlled oscillator and a phase-lock loop using the voltage-controlled oscillator. The Campbell disclosure is useful for decoding Manchester data. The disclosure identifies a phase-lock loop which has a narrow bandwidth and a fast acquisition time. This disclosure hereby incorporates by reference the Campbell patent for all purposes.
The Campbell patent is useful in Manchester decoding apparatus because it establishes a narrow bandwidth phase-lock loop locked onto an external 10 MHz frequency source. When it is desired to decode an incoming Manchester signal, the phase-lock loop operating at the external 10 megahertz reference frequency is temporarily interrupted, the Manchester signal is switched in place of the external reference clock, and the phase-lock loop is then caused to resume operation at a specific phase of the Manchester signal. Thereafter, acquisition is virtually immediate as the phase-lock loop is operating at the nominal 10 megahertz frequency and the phase difference between the phase-lock loop and the embedded 10 megahertz Manchester-encoded clock is virtually zero. As the phase-lock loop has a narrow bandwidth, it is not susceptible to the 5 megahertz component and will continue sampling the data at the 10 MHz embedded clock frequency.
The Campbell invention uses a master-slave phase-lock loop configuration. The Campbell patent incorporates power intensive emitter coupled logic (ECL) to implement the invention. It is desired to provide a narrow bandwidth fast acquisition phase-lock loop from complementary metal oxide semiconductor (CMOS) structures. Additionally, elimination of structures in the Campbell implementation reduces component count.